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-- Company: GVSU
-- Engineering Student: Paul Shields
-- 
-- Create Date:    18:14:25 01/21/2010 
-- Design Name: 
-- Module Name:    Multiplexer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
-- This multiplexes an 8 bit input signal over a 4 bit output with a 4 bit address select
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SevenSegMultiplexer is
    Port (	reset : in STD_LOGIC;
				clk : in STD_LOGIC;
				input0 : in  STD_LOGIC_VECTOR (3 downto 0);
				input1 : in  STD_LOGIC_VECTOR (3 downto 0);
				output0 : out  STD_LOGIC_VECTOR (3 downto 0);
				anselect : out STD_LOGIC_VECTOR (3 downto 0));
			  
end SevenSegMultiplexer;

architecture Behavioral of SevenSegMultiplexer is
-- Only the first two seven segment displays are used and so their are only two cases
SIGNAL clk_div : UNSIGNED(16 downto 0);
begin

--divide 50MHz clk to get 763Hz divclk
	ClockDivider : PROCESS (reset, clk)
	BEGIN
		IF reset = '1' THEN
			clk_div <= "00000000000000000";
		ELSIF rising_edge(clk) THEN
			clk_div <= clk_div + 1;
		END IF;
	END PROCESS;

process(reset, clk_div(16))
variable temp : integer range 0 to 1;
begin
	IF reset = '1' THEN
		anselect <= "1111";
		output0 <= "1111";
		temp := 0;
	
	ELSIF (rising_edge(clk_div(16))) then
		-- if the temp is at 0 then
		if(temp=0) then
			-- set output
			output0 <= input0;
			-- turn on the right most seven segment digit
			anselect <= "1110";
			-- increment the counter
			temp:=temp+1;
		-- if temp is 1
		else
			-- set output
			output0 <= input1;
			-- turn on the second seven segement digit
			anselect <= "1101";
			-- reset the counter
			temp:=0;
		end if;
	end if;
end process;

end Behavioral;